A behavior-based reconfigurable cache for the low-power embedded processor.
Jiongyao YeJiannan JinTakahiro WatanabePublished in: ASICON (2011)
Keyphrases
- low power
- embedded processors
- single chip
- low cost
- power consumption
- high speed
- power reduction
- hardware and software
- high power
- digital signal processing
- wireless transmission
- signal processor
- embedded systems
- dynamic random access memory
- image sensor
- vlsi architecture
- low power consumption
- gate array
- real time
- power dissipation
- parallel implementation
- mixed signal
- field programmable gate array
- power management
- hardware implementation
- signal processing