A 211 GOPS/W dual-mode real-time object recognition processor with Network-on-Chip.

Kwanho Kim Joo-Young Kim Seungjin Lee Minsu Kim Hoi-Jun Yoo

Published in: ESSCIRC (2008)

Keyphrases

real time
object recognition
multi processor
network on chip
high speed
computer vision
packet switched
low cost
single processor
data acquisition
parallel processing
bit rate
routing algorithm
parallel architectures