2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control.
Yoshichika FujiokaMichitaka KameyamaPublished in: ICRA (3) (1993)
Keyphrases
- robot control
- parallel processing
- systolic array
- single chip
- distributed memory
- mobile robot
- autonomous robots
- computer architecture
- single processor
- high speed
- multi core processors
- digital signal
- subsumption architecture
- unstructured environments
- gate array
- parallel architectures
- low cost
- low power
- parallel architecture
- processor array
- level parallelism
- motion control
- parallel programming
- parallel processors
- parallel implementation
- parallel computers
- processing elements
- shared memory
- hardware implementation
- signal processing
- neural network
- massively parallel
- parallel computing
- functional units
- chip design
- objective function
- machine learning