A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS.
Athanasios T. RamkajJuan Carlos Pena RamosMarcel J. M. PelgromMichiel S. J. SteyaertMarian VerhelstFilip TavernierPublished in: IEEE J. Solid State Circuits (2020)
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