A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS.
Athanasios T. RamkajJuan Carlos Pena RamosMarcel J. M. PelgromMichiel S. J. SteyaertMarian VerhelstFilip TavernierPublished in: IEEE J. Solid State Circuits (2020)
Keyphrases
- analog to digital converter
- delta sigma
- mixed signal
- wide dynamic range
- dynamic range
- circuit design
- power consumption
- cmos image sensor
- cmos technology
- low power
- image sensor
- sigma delta
- single chip
- analog vlsi
- metal oxide semiconductor
- image reconstruction
- electro optic
- synthetic aperture radar
- power supply
- hd video
- sar images
- multi channel
- power dissipation
- parallel processing
- high dynamic range
- random sampling
- solid state
- low cost
- nm technology
- high speed