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A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS.

Bindi WangYao-Hong LiuPieter HarpeJohan H. C. van den HeuvelBo LiuHao GaoRobert Bogdan Staszewski
Published in: ISCAS (2015)
Keyphrases
  • phase locked loop
  • ultra low power
  • camera calibration
  • circuit design
  • low cost
  • high speed
  • user friendly
  • data conversion
  • control method
  • metal oxide semiconductor