Efficient and Scalable Architecture for Multiple-chip Implementation of Simulated Bifurcation Machines.
Tomoya KashimataMasaya YamasakiRyo HidakaKosuke TatsumuraPublished in: CoRR (2023)
Keyphrases
- vlsi implementation
- efficient implementation
- highly scalable
- layered architecture
- low cost
- real time
- lightweight
- high speed
- hardware implementation
- highly optimized
- signal processor
- host computer
- analog vlsi
- hardware architecture
- circuit design
- reconfigurable hardware
- design considerations
- memory efficient
- high density