Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits.
Yuvraj Singh DhillonAbdulkadir Utku DirilAbhijit ChatterjeeCecilia MetraPublished in: IOLTS (2005)
Keyphrases
- circuit design
- chip design
- logic synthesis
- high speed
- delay insensitive
- optimal design
- high level synthesis
- logic circuits
- cmos technology
- power dissipation
- digital circuits
- load balancing
- low voltage
- optimization algorithm
- analog vlsi
- design space
- global optimization
- power consumption
- design process
- logic programming
- random access memory
- optimization problems
- low power
- power supply
- vlsi circuits
- floating gate
- user interface