A high speed CMOS/SOS implementation of a bit level systolic correlator.

J. C. White John V. McCanny A. McCabe John G. McWhirter R. Evans

Published in: ICASSP (1986)

Keyphrases

high speed
low power
bit parallel
higher level
frame rate
shift register
random access memory
circuit design
real time
low cost
multiscale
image processing
efficient implementation
levels of abstraction
multiresolution
focal plane
cmos technology
case study