Login / Signup

Dual PN Source/Drain Reconfigurable FET for Fast and Low-Voltage Reprogrammable Logic.

Carlos NavarroCarlos MarquezSantiago NavarroFrancisco Gámiz
Published in: IEEE Access (2020)
Keyphrases
  • low voltage
  • random access memory
  • design considerations
  • power line
  • low cost
  • petri net
  • chip design
  • cmos technology
  • hardware implementation
  • power management
  • response time