An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS.
Kentaro YoshiokaAkira ShikataRyota SekimotoTadahiro KurodaHiroki IshikuroPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2015)