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) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators.
Taro Niiyama
Piao Zhe
Koichi Ishida
Masami Murakata
Makoto Takamiya
Takayasu Sakurai
Published in:
ISLPED (2008)
Keyphrases
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small number
fixed number
experimental verification
computational complexity
neural network
image processing
website
search algorithm
high speed
low power
automated reasoning
delay insensitive