A Loop Optimization Technique for Speculative Chip Multiprocessors.
Chao-Chin WuKuan-Chou LaiPublished in: IWNAS (2006)
Keyphrases
- multithreading
- high speed
- distributed memory
- low cost
- analog vlsi
- programmable logic
- parallel implementation
- high density
- single chip
- instruction scheduling
- evolvable hardware
- physical design
- parallel computing
- solid models
- real time
- vlsi implementation
- vlsi design
- feedback loop
- highly parallel
- high bandwidth
- computational power
- shared memory
- highly efficient
- operating system
- neural network