VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams.

Andrzej Pulka Adam Milik

Published in: FDL (2008)

Keyphrases

unified modeling language
asynchronous circuits
class diagram
sequence diagrams
neural network
object oriented
uml diagrams
uml class diagrams
class diagrams
database
software development
model checking
development process
graphical representation
signature verification