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Design and hardware implementation of digital channel selection decimating filter for multistandard receiver.
Khaled Grati
Adel Ghazel
Lirida A. B. Naviner
Published in:
ICECS (2005)
Keyphrases
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hardware implementation
hardware design
efficient implementation
fpga implementation
signal processing
hardware architecture
machine learning
pattern recognition
fpga device
computer vision
field programmable gate array
software implementation
memory management
dedicated hardware