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A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS.

Akira ShikataRyota SekimotoTadahiro KurodaHiroki Ishikuro
Published in: IEEE J. Solid State Circuits (2012)
Keyphrases
  • high speed
  • levels of abstraction
  • single chip
  • analog vlsi
  • denoising
  • low cost
  • post processing
  • sar images
  • vlsi circuits
  • cmos image sensor