A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism.

Ching-Hwa Cheng Jiun-In Guo

Published in: VLSI-DAT (2012)

Keyphrases

circuit design
high speed
real time
design automation
data acquisition
parallel architecture
low power
focal plane
signal acquisition
high frame rate
computational model
training phase
high speed networks
processing capabilities
case study
image processing
information systems
data sets