Hierarchical Statistical Verification of Large Full Custom CMOS Circuits.
A. B. van der WalRobert G. J. ArendsenAarnout BrombacherO. E. HerrmannPublished in: ISCAS (1994)
Keyphrases
- delay insensitive
- analog vlsi
- high speed
- asynchronous circuits
- circuit design
- vlsi circuits
- low cost
- domain specific
- cmos technology
- data driven
- statistical analysis
- power dissipation
- low power
- random access memory
- focal plane
- hierarchical model
- coarse to fine
- power consumption
- hierarchical structure
- statistical models
- model checking
- neural network
- application specific
- confidence intervals
- power supply
- data sets
- machine learning