FPGA based realization of a reduced complexity high speed decoder for error correction.

Shuja Ahmad Abbasi

Published in: ICECS (2003)

Keyphrases

error correction
reduced complexity
high speed
reed solomon
error control
ldpc codes
turbo codes
noisy channel
error detection
vector quantization
low density parity check
channel coding
error analysis
error resilient
low complexity
motion estimation algorithm
frame rate
bit errors
watermarking scheme
computer vision