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Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications.
Ming-Dou Ker
Shih-Lun Chen
Chia-Sheng Tsai
Published in:
ISCAS (2) (2005)
Keyphrases
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high voltage
phase locked loop
data mining
artificial neural networks
operating conditions
circuit design
knowledge base
expert systems
evolutionary algorithm
semi supervised
power system
input output
evolutionary computation
partial discharge