Login / Signup
A 12.88 MS/s 0.28 pJ/conv.step 8-bit stage-interleaved pulse-shrinking time-to-digital converter in 130 nm CMOS.
Young Jun Park
Fei Yuan
Published in:
MWSCAS (2015)
Keyphrases
</>
analog to digital converter
low voltage
mixed signal
cmos technology
metal oxide semiconductor
learning stage
low power
circuit design
cmos image sensor
data conversion
random access memory
post processing
image sensor
low cost
transfer function
preprocessing stage
design considerations
metadata
multi channel
video coding
vlsi circuits