A modified architecture used for input matching in CMOS low-noise amplifiers.
Shouxian MouJianguo MaKiat Seng YeoManh Anh DoPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2005)
Keyphrases
- input data
- high noise
- low signal to noise ratio
- management system
- high speed
- analog vlsi
- image matching
- matching process
- matching algorithm
- software architecture
- power consumption
- missing data
- additive noise
- low cost
- row column
- pattern matching
- neural network
- signal noise ratio
- real time
- power supply
- random noise
- network architecture
- noise level
- signal to noise ratio