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A 1.7-2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS.
Matteo Ramella
Ivan Fabiano
Danilo Manstretta
Rinaldo Castello
Published in:
A-SSCC (2015)
Keyphrases
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power consumption
silicon on insulator
clock gating
high speed
cmos technology
low power
nm technology
power management
clock frequency
low cost
power dissipation
power reduction
power saving
delay insensitive
metal oxide semiconductor
power distribution
ibm power processor