Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks.

Andrzej Krasniewski

Published in: IOLTS (2004)

Keyphrases

error detection
error correction
embedded systems
error recovery
data cleansing
error correcting
memory requirements
smart camera
high speed
hardware implementation
field programmable gate array
fault isolation
sensor networks
reconfigurable hardware
read write
fault tolerance
main memory
low cost