Highly Efficient Test Architecture for Low-Power AI Accelerators.
Muhammad IbtesamUmair Saeed SolangiJinuk KimMuhammad Adil AnsariSungju ParkPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2022)
Keyphrases
- highly efficient
- low power
- low cost
- single chip
- vlsi architecture
- power consumption
- high speed
- real time
- multithreading
- cmos technology
- cmos image sensor
- nm technology
- low complexity
- high power
- low power consumption
- signal processor
- hardware and software
- wireless transmission
- mixed signal
- vlsi circuits
- digital camera
- logic circuits
- embedded systems
- computing platform
- power reduction
- image sensor
- vlsi implementation
- orders of magnitude
- computing systems
- image processing