A compact low-power VLSI architecture for real-time sleep stage classification.

Peter Zhi Xuan Li Hossein Kassiri Roman Genov

Published in: ISCAS (2016)

Keyphrases

vlsi architecture
low power
sleep stage
power consumption
real time
low cost
high speed
low complexity
vlsi implementation
sleep apnea
low power consumption
pattern recognition
feature vectors
signal processing
image compression
mixed signal