A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS.
Xiaobao YuBaoyong ChiMeng WeiAlbert Z. WangTianling RenZhihua WangPublished in: ISCAS (2013)
Keyphrases
- high speed
- high data rate
- power consumption
- data acquisition
- clock gating
- power dissipation
- low power
- cmos technology
- clock frequency
- communication systems
- nm technology
- low cost
- communication networks
- analog vlsi
- silicon on insulator
- power reduction
- focal plane
- real time
- metal oxide semiconductor
- image sensor
- frequency band
- focal length