Semi-formal Verification of the quasi-static behavior of Mixed-Signal Circuits by SAT-based Property Checking.
Martin FreibotheJens SchönherrBernd StraubeJörg BormannPublished in: ISoLA (Preliminary proceedings) (2004)
Keyphrases
- formal verification
- bounded model checking
- mixed signal
- quasi static
- vlsi circuits
- low power
- model checking
- multi channel
- digital circuits
- high speed
- cmos technology
- power consumption
- temporal logic
- image analysis
- finite state machines
- linear temporal logic
- power dissipation
- displacement field
- planning domains
- end to end
- deformable models
- computer simulation
- image registration