A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS.

Xianshan Wen Tao Fu Liang Fang Ping Gui

Published in: IEEE Access (2024)

Keyphrases

analog to digital converter
high speed
nm technology
sar images
synthetic aperture radar
single chip
cmos technology
random access memory
low power
power consumption
multiscale
analog vlsi