Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology.

Yibai He Shuming Chen

Published in: Sci. China Inf. Sci. (2014)

Keyphrases

cmos technology
flip flops
low power
power dissipation
silicon on insulator
spl times
power consumption
parallel processing
low voltage
low cost
multiple input
image sensor