Generic and Universal Parallel Matrix Summation with a Flexible Compression Goal for Xilinx FPGAs.
Thomas B. PreußerPublished in: CoRR (2018)
Keyphrases
- field programmable gate array
- hardware implementation
- parallel computing
- high speed
- pipelined architecture
- image compression
- massively parallel
- compression scheme
- parallel processing
- fpga implementation
- linear algebra
- parallel architectures
- compression ratio
- embedded systems
- shared memory
- processing elements
- parallel implementation
- hardware design
- computer architecture
- singular value decomposition
- domain specific