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Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design.
Jianan Mu
Huajie Tan
Shuai Chen
Min Cai
Jing Ye
Huawei Li
Xiaowei Li
Published in:
ATS (2023)
Keyphrases
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high level
hardware architecture
design process
circuit design
low level
low cost
embedded systems
image processing
engineering design
hardware design
single chip
user interface
high level abstraction
source code
cellular automata
computing systems
high speed
programmable logic