Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process.

Karthik Rajagopal

Published in: ISQED (2012)

Keyphrases

low power
power consumption
high speed
low cost
cmos technology
low power consumption
single chip
nm technology
delay insensitive
vlsi circuits
image sensor
logic circuits
wireless transmission
signal processor
ultra low power
mixed signal
error correction