Design of Baseband Analog with Filter Tuning for 5.8GHz DSRC Transceiver in ETCS.

Ji Hoon Song Kang-Yoon Lee

Published in: ICUFN (2021)

Keyphrases

case study
high speed
circuit design
fir filters
multiscale
design process
noise reduction
digital circuits
filter design
vlsi architecture
phase locked loop