A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder.
Wei-Li SuHerming ChiuehPublished in: ICECS (2006)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- noisy channel
- power dissipation
- single chip
- high power
- logic circuits
- decoding algorithm
- hidden markov models
- power reduction
- vlsi circuits
- wireless transmission
- edge detection
- vlsi architecture
- cmos technology
- error concealment
- gate array
- mixed signal
- nm technology
- ultra low power
- digital signal processing
- error resilient
- image sensor
- random access
- low complexity
- motion estimation