A Layout Area Reduction of Basic Logic Element by Using a Neuron CMOS Type 4-input Variable Logic Circuit.
Shoma ItoHisaya SawadaHirotaka FurukawaNaruaki HokariDaishi NishiguchiMasaaki FukuharaPublished in: TENCON (2023)
Keyphrases
- delay insensitive
- flip flops
- high speed
- digital circuits
- modal logic
- logic circuits
- logic programming
- chip design
- logic synthesis
- low power
- classical logic
- multiple input
- asynchronous circuits
- circuit design
- low cost
- analog vlsi
- multiple output
- predicate logic
- truth table
- proof theory
- real time
- defeasible logic
- bayesian networks
- neural network