A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays.
Yin-Tsung HwangYu Hen HuPublished in: J. VLSI Signal Process. (1995)
Keyphrases
- multistage
- iterative algorithms
- lot sizing
- production system
- dynamic programming
- stochastic optimization
- stochastic programming
- attack detection
- scheduling problem
- single stage
- parallel processors
- multiprocessor systems
- optimal policy
- production planning
- dual formulation
- partitioning schemes
- production line
- round robin
- resource allocation