A Scalable Low-Power Reconfigurable Accelerator for Action-Dependent Heuristic Dynamic Programming.
Nan ZhengPinaki MazumderPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2018)
Keyphrases
- low power
- dynamic programming
- low cost
- power consumption
- high speed
- power reduction
- high power
- single chip
- low power consumption
- wireless transmission
- lagrangian relaxation
- field programmable gate array
- vlsi circuits
- logic circuits
- vlsi architecture
- hardware and software
- cmos technology
- image sensor
- digital camera
- digital signal processing
- delay insensitive
- compute intensive
- gate array
- stereo matching
- signal processing
- mixed signal
- general purpose
- image processing
- ultra low power
- parallel implementation
- reinforcement learning