FPGA timing, power, signal integrity and other challenges at 65 and 45 nm.
Paul LeventisPublished in: FPT (2008)
Keyphrases
- signal processing
- digital signal
- power reduction
- high frequency
- lessons learned
- key issues
- hardware implementation
- high speed
- real time image processing
- duty cycle
- open issues
- power consumption
- impulse response
- heart rate
- frequency domain
- low cost
- original signal
- signal detection
- real time
- silicon on insulator
- radio frequency
- hardware design
- field programmable gate array
- low power
- integrity constraints
- real world
- neural network