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1.5-3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in 0.13~µm CMOS.
Erkan Bayram
Ahmed Farouk Aref
Mohamed Saeed Elsayed
Renato Negra
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2018)
Keyphrases
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power consumption
clock frequency
low power
power supply
power dissipation
high speed
circuit design
dead zone
hd video
dielectric constant
cmos technology
dual band
charge coupled device
waveguide
neural network
weight update
fuzzy logic
mobile robot
artificial neural networks
genetic algorithm