A CAD methodology for optimizing transistor current and sizing in analog CMOS design.
David M. BinkleyC. E. HopperSteve D. TuckerBrian C. MossJames M. RochelleDaniel FotyPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2003)
Keyphrases
- circuit design
- high speed
- design process
- design methodology
- computer aided
- low power
- analog vlsi
- single chip
- computer aided design
- object oriented
- power supply
- conceptual framework
- power consumption
- software architecture
- real time
- current status
- design considerations
- building blocks
- low cost
- power dissipation
- vlsi architecture
- digital computer
- soft systems