A Fault Tolerant Hierarchical Network on Chip Router Architecture.

Mohammad Hossein Neishaburi Zeljko Zilic

Published in: J. Electron. Test. (2013)

Keyphrases

network on chip
fault tolerant
interconnection networks
fault tolerance
routing algorithm
multi processor
packet switched
distributed systems
network simulator
load balancing
wireless sensor networks
data transfer
parallel algorithm
message passing
power dissipation