High-speed dynamic dual-rail ultra low voltage static CMOS logic operating at 300 mV.

Omid Mirmotahari Ali Dadashi Mehdi Azadmehr Yngvar Berg

Published in: DTIS (2016)

Keyphrases

high speed
low voltage
low power
random access memory
cmos technology
power line
real time
frame rate
design considerations
mixed signal
multi valued