Hardware implementation of the median-rational hybrid filters.
Giuseppe BernacchiaLazhar KhrijiMoncef GabboujGiovanni L. SicuranzaPublished in: ICECS (1999)
Keyphrases
- hardware implementation
- median filter
- signal processing
- efficient implementation
- software implementation
- fpga implementation
- image processing algorithms
- dedicated hardware
- pipeline architecture
- hardware design
- hardware architecture
- field programmable gate array
- parallel architecture
- memory management
- fpga device
- image binarization
- pipelined architecture
- pattern recognition
- edge detection