A 372 ps 64-bit adder using fast pull-up logic in 0.18µm CMOS.
Joo-Young KimKangmin LeeHoi-Jun YooPublished in: ISCAS (2006)
Keyphrases
- random access memory
- flip flops
- delay insensitive
- logic circuits
- power dissipation
- low voltage
- design considerations
- low power
- bit parallel
- logical operations
- low cost
- power consumption
- pattern matching
- modal logic
- chip design
- logic programming
- predicate logic
- data sets
- analog to digital converter
- cmos technology
- automated reasoning
- high speed