• search
    search
  • reviewers
    reviewers
  • feeds
    feeds
  • assignments
    assignments
  • settings
  • logout

Port assignment for interconnect reduction in high-level synthesis.

Cong HaoSong ChenTakeshi Yoshimura
Published in: VLSI-DAT (2012)
Keyphrases
  • high level synthesis
  • high speed
  • parallel architecture
  • machine learning
  • design space exploration
  • information systems