A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications.
Michael ClintonRajinder SinghMarty TsaiShayan ZhangBryan SheffieldJonathan ChangPublished in: ISSCC (2018)
Keyphrases
- mobile applications
- high speed
- mobile devices
- main memory
- mobile phone
- memory hierarchy
- m learning
- user experience
- low power
- mobile users
- smart phones
- context aware
- cache conscious
- gigabit ethernet
- mobile environments
- mobile services
- end users
- wireless devices
- garbage collection
- mobile technologies
- memory access
- location based services
- memory subsystem
- memory management
- battery life
- level parallelism
- mobile apps
- mobile platforms
- virtual memory
- computational power
- cache misses
- dynamic random access memory
- location awareness
- mobile learning