Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench.
Yingyi LuoXianshan WenKazutomo YoshiiSeda Ogrenci MemikGokhan MemikHal FinkelFranck CappelloPublished in: FPL (2017)
Keyphrases
- memory access
- shared memory
- field programmable gate array
- parallel computing
- data access
- parallel algorithm
- memory management
- hardware implementation
- external memory
- high volume
- case study
- main memory
- message passing
- real time
- cache misses
- processing units
- parallel programming
- low cost
- access patterns
- data management
- management system