A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation.
Ja-Yol LeeMi-Jeong ParkByung-Hun MinSeongdo KimMun-Yang ParkHyun-Kyu YuPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2012)
Keyphrases
- low power
- error compensation
- high speed
- mixed signal
- power consumption
- low cost
- vlsi circuits
- single chip
- wireless transmission
- digital signal processing
- high power
- gate array
- low power consumption
- image sensor
- multi channel
- logic circuits
- power reduction
- structured light
- power dissipation
- cmos image sensor
- signal processor
- real time
- power saving
- delay insensitive