A throughput maximised parallel architecture for 2D fast Discrete Pascal Transform.

Ming Ming Wong M. L. Dennis Wong Ismat Hijazin

Published in: Comput. Electr. Eng. (2010)

Keyphrases

parallel architecture
parallel processing
translation invariant
response time
systolic array
hardware implementation
shared memory
high level synthesis
parallel implementation
hartley transform
distributed memory
discrete fourier transform
clock frequency
lower bound
higher order