On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches.
Qiang YangJian FuRaphael PossChris R. JesshopePublished in: ACM Trans. Embed. Comput. Syst. (2014)
Keyphrases
- bandwidth consumption
- network on chip
- hierarchical architecture
- distributed architecture
- network simulator
- communication cost
- memory access
- lightweight
- real time
- wide area network
- loosely coupled
- distributed processing
- analog vlsi
- network devices
- high speed
- overlay network
- communication protocol
- peer to peer
- vlsi implementation
- ip address
- network layer
- level parallelism
- texas instruments
- distributed environment
- low cost
- multi agent
- single chip
- network traffic
- distributed systems